In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continue to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required storage capabilities is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, planarized layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining high dielectric breakdown between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi, entitled "3- DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS," IEDM, Dig. Tech. Papers, pp. 592-595, 1988, herein incorporated by reference, discusses a 3-dimensional stacked capacitor fin structure.
The fin structure and its development is shown in FIG. 1, pp. 593 of the article mentioned above. The storage node is formed by two polysilicon layers, called fins, with gaps between the fins (the number of fins can be increased, but is limited by design rules used). Capacitor dielectric film surrounds the whole surface of the fins with polysilicon (used for a capacitor cell plate) covering the fins and filling in the gaps. This design can be fabricated using current methods and increases storage capacitance, but it is not suitable for a deep submicron (such as 0.2 micron) design rule DRAM cell because the total thickness of several fins and cell plate is much larger than minimum feature size. The process flow, needed to realize this fin structure, requires precise alignment between two adjacent word lines and digits lines. This alignment along with the requirement to have the storage node poly overlap the storage node contact leads to a larger cell area that is not suitable for 0.2 micron design rules mentioned previously.
Also, in a paper submitted by S. Inoue, K. Hieda, A. Nitayama, F. Horiguchi and F. Masuoka, entitled "A SPREAD STACKED CAPACITOR (SSC) CELL FOR 64MBIT DRAMS," IEDM, Dig. Tech. Papers, pp. 31-34, 1989, herein incorporated by reference, discusses a storage electrode of a 1st memory cell being expanded to the neighboring 2nd memory cell area.
The SSC cell fabrication process (refer to FIG. 2 pp. 32) begins with a storage electrode deposited above the digit lines that is expanded from the 1st memory cell to its adjacent memory cells and visa versa. This results in a stacked capacitor arrangement where each storage electrode can occupy two memory cell areas, thus almost doubling the storage capacitance of one memory cell.
However, the SSC process is complicated and adds at least two masks to the standard process and cannot be made with self-aligned contacts.
The present invention develops an existing stacked capacitor fabrication process to construct a three-dimensional stacked capacitor cell by using self aligned contacts without additional photolithography steps.